Current microprocessor designs need to centralize data transfer operations under control of integrated functional units known as data transfer access units or enhanced direct memory access (EDMA) units. EDMA is of most interest here and specifically of interest are EDMA designs employing hub-and-port style architecture. Such EDMAs feature a hub unit, which maintains a queue of transfer requests and provides priority protocol and proper interfacing for the handling of a large number of such requests. Secondly hub-and-port EDMAs have one or more hub interface units (HIU), which each provide a seamless interface between the EDMA hub and its ports. Ports are typically external application units (AU) otherwise known as peripheral units. Internal memory ports are also included among the EDMA ports.
FIG. 1 illustrates the essentials of a prior art microprocessor system having EDMA 100 and central processing unit (CPU) 101. EDMA 100 includes transfer controller 102 and hub interface units (HIU) 104, 105, and 106. Communication between the transfer controller hub unit 102 and HIUs 104, 105, and 106 employs buses 103, 107, 108, 109, and 110. Each HIU provides interface to a single port. Peripheral unit 114 and 115 communication with corresponding HIUs 104 and 105 via respective paths 111 and 112. The microprocessor system also includes the internal memory port device 116 which communications with HIU 106 via path 113. The EDMA 100 responds to transfer requests not only from CPU 101 but also from any of the ports it services. Transfer requests (TR) handled by transfer controller (TC) hub unit 102 involve transfer of data from one port to another. Transfer commands reside in transfer request packets that give all the detailed parameters of a transfer.
FIG. 2 illustrates the functional units of the transfer controller portion of EDMA 200 (prior art). The transfer request processor 201 receives transfer requests from CPU 230 and from one or more HIU 210 via path 228. Transfer request processor 201 passes these requests to queue manager 202. Queue manager 202 receives data transfer request packets (TRP), places them in queue manager RAM 203 and assigns them to one of the P channel priority levels. It is helpful to distinguish TRPs stored in the queue manager RAM 203 as being in the queue, and TRPs stored in the channel registers block 204 as being active. For example, for N=32, EDMA 200 could have four channel priorities and channel register block 204 could hold eight active transfer packets at each priority level. At any given time channel register block 204 could hold up to 32 total TRPs.
If there is no channel available for direct processing of a TRP coming into queue manager 202, it is stored in queue manager RAM 203. The TRP is then submitted to the channel registers 204 at a later time when a channel becomes available. Source ready signal 213 and destination ready signal 215 indicate availability of a channel space within the channel registers 204. Channel registers 204 interface with source pipeline 205 and destination pipeline 206. Source pipeline 205 and destination pipeline 206 are address calculation units for source (read) and destination (write) operations. These pipelines broadcast outputs to M ports of EDMA 200 through M hub interface units 210, which drive the M possible external ports units. FIG. 2 illustrates just one port 229 as an example. When source pipeline space is available, source pipeline 204 passes source ready signal 216 to the channel registers 204, which passes source ready signal 213 to queue manager 202. When destination pipeline space is available, destination pipeline 206 passes destination ready signal 219 to the channel registers 204, which passes destination ready signal 215 to queue manager 202. Queue manager block 202 passes source read commands developed from the transfer packets to channel registers 204 via path 214 and hence to source pipeline 205 via path 217. Queue manager block 202 passes destination write commands developed from the transfer packets to channel registers 204 via path 214 and hence to destination pipeline 205 via path 220. Source valid signal 218 and destination valid signal 221 from channel registers 204 alert the respective pipelines that a valid transfer is ready to be processed.
Signals broadcast from transfer controller (TC) to the hub interface units (HIU) 210 and returning from the HIU to the TC include: source read command 222; destination write command 223; destination write data 224; read response information 227 from HIU to read response FIFO buffer 208; read return data from ports 225 to be stored in write data FIFO buffer 207; TC acknowledge flag 226 from response acknowledge logic 209 to HIU 210.